This invention relates to a CMOS type programmable logic array, and more particularly to regenerative strobe circuitry for a multi-input CMOS logic gate circuit which is used as the basis of a logic array.
Digital logic circuits such as NOR gates are well known in the art. Typically, a NOR gate consists of a plurality of transistors connected in a parallel manner between independent input signals and a fixed potential. Each transistor is turned on or off depending on the difference of potential seen by the transistor between the input signal and the fixed potential. The use of a plurality of NOR gates permits the execution of various logic functions in a compact manner. Indeed, such a use of NMOS NOR gates in a programmable logic array is well known and permits an elegant solution at most any clocking speed for decoding the sum of products. The drawback to the NMOS NOR gate arrangement, however, has always been that the NMOS NOR gates dissipate an excessive amount of power. CMOS ciurcuits for the NOR gate arrangement have been disclosed by e.g. U.S Pat. Nos. 4,053,792, to Cannistra et al and 3,911,289, to Takemoto and they do limit power dissipation, but neither patent discloses a circuit which eliminates power dissipation completely during active (non-strobing) periods of the logic array.
Digital logic AND and OR gates are also well known in the art for decoding a sum of products. In fact, dynamic CMOS AND and OR gates have provided a solution to the power dissipation problems of the NMOS NOR gate arrangement. However, the CMOS AND-OR gate solution brings its own difficulties into play. One problem with the CMOS logic array arrangements is that the output from the AND plane floats during the active phase, thereby limiting the lowest clock speed at which the logic array may be strobed (e.g. clock rate&gt;100 KHz). Another problem is that if the clocks are stopped, large amounts of current can flow with possible damage to the array resulting unless careful consideration is given to internal floating logic states. While additional circuitry such as flip-flops and latches have been used to reduce the seriousness of the latter problem, the former problem is not easily solved.
It is therefore a primary object of the invention to provide a circuit for a logic array which dissipates power only during strobing and which regenerates the output after strobing.
It is a further object of this invention to provide a regenerative strobe circuit for a CMOS programmable logic array which dissipates power only during strobing.
Another object of this invention is to provide a regenerative strobe circuit for a multi-input NOR gate circuit which dissipates power only during strobing and which has a low number of elements which operate rapidly.